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MC33363A High Voltage Switching Regulator
The MC33363A is a monolithic high voltage switching regulator that is specifically designed to operate from a rectified 240 Vac line source. This integrated circuit features an on-chip 700 V / 1.5 A SENSEFETt power switch, 500 V active off-line startup FET, duty cycle controlled oscillator, current limiting comparator with a programmable threshold and leading edge blanking, latching pulse width modulator for double pulse suppression, high gain error amplifier, and a trimmed internal bandgap reference. Protective features include cycle-by-cycle current limiting, input undervoltage lockout with hysteresis, output overvoltage protection, and thermal shutdown. This device is available in a 16-lead dual-in-line and wide body surface mount packages.
Features
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PDIP-16 P SUFFIX CASE 648E 16 1
MC33363AP AWLYYWWG
* * * * * * * * * * *
Enhanced Power Capability Over MC33363 On-Chip 700 V, 1.5 A SENSEFET Power Switch Rectified 240 Vac Line Source Operation On-Chip 500 V Active Off-Line Startup FET Latching PWM for Double Pulse Suppression Cycle-By-Cycle Current Limiting Input Undervoltage Lockout with Hysteresis Output Overvoltage Protection Comparator Trimmed Internal Bandgap Reference Internal Thermal Shutdown Pb-Free Packages are Available*
16 1 A WL YY WW G
SO-16W DW SUFFIX CASE 751N
MC33363ADW AWLYYWWG
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
PIN CONNECTIONS
AC Input Startup Input Regulator Output 8 6 RT CT OSC 7 PWM Latch S Q PWM R Ipk Thermal LEB Driver OVP Startup Reg UVLO VCC 3 Overvoltage Protection Input 11 16 Power Switch Drain DC Output 1
Startup Input
1
16
Power Switch Drain
Mirror
VCC GND
3 4 5 13 GND 12 11 10 9 (Top View) Overvoltage Protection Input Voltage Feedback Input Compensation
RT CT Regulator Output
6 7 8
ORDERING INFORMATION
Compensation 9 EA 10 See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet.
GND
Voltage Feedback 4, 5, 12, 13 Input This device contains 221 active transistors.
Figure 1. Simplified Application
(c) Semiconductor Components Industries, LLC, 2005
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 1 Publication Order Number: MC33363A/D
November, 2005 - Rev. 5
MC33363A
MAXIMUM RATINGS (Note 1)
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Power Switch (Pin 16) Drain Voltage Drain Current VDS IDS Vin 700 1.5 500 40 V A V V V Startup Input Voltage (Pin 1) Power Supply Voltage (Pin 3) VCC VIR Input Voltage Range Voltage Feedback Input (Pin 10) Compensation (Pin 9) Overvoltage Protection Input (Pin 11) RT (Pin 6) CT (Pin 7) -1.0 to Vreg Thermal Characteristics - P Suffix, Dual-In-Line Case 648E Thermal Resistance, Junction-to-Air Thermal Resistance, Junction-to-Case (Pins 4, 5, 12, 13) C/W RqJA RqJC RqJA RqJC 80 15 95 15 DW Suffix, Surface Mount Case 751N Thermal Resistance, Junction-to-Air Thermal Resistance, Junction-to-Case (Pins 4, 5, 12, 13) Refer to Figures 17 and 18 for additional thermal information. Operating Junction Temperature Storage Temperature TJ -25 to +150 -55 to +150 C C Tstg Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per MIL-STD-883, Method 3015. Machine Model Method 150 V.
Rating
Symbol
Value
Unit
ELECTRICAL CHARACTERISTICS (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin8 = 1.0 mF, for typical values TJ = 25C, for min/max
values TJ is the operating junction temperature range that applies (Note 2), unless otherwise noted) Characteristic Symbol Min Typ Max Unit
REGULATOR (Pin 8)
Output Voltage (IO = 0 mA, TJ = 25C) Line Regulation (VCC = 20 V to 40 V)
Vreg
5.5 - -
6.5 30 44 -
7.5
V
Regline
500 200 8.0
mV mV V
Load Regulation (IO = 0 mA to 10 mA)
Regload Vreg
Total Output Variation over Line, Load, and Temperature
5.3
OSCILLATOR (Pin 7)
Frequency CT = 390 pF TJ = 25C (VCC = 20 V) TJ = Tlow to Thigh (VCC = 20 V to 40 V) CT = 2.0 nF TJ = 25C (VCC = 20 V) TJ = Tlow to Thigh (VCC = 20 V to 40 V)
fOSC
kHz
260 255 60 59 -
285 -
310 315 75 76
67.5 - 0.1
Frequency Change with Voltage (VCC = 20 V to 40 V)
DfOSC/DV
2.0
kHz
ERROR AMPLIFIER (Pins 9, 10)
Voltage Feedback Input Threshold
VFB
2.52 - - -
2.6 0.6 20 82
2.68 5.0
V
Line Regulation (VCC = 20 V to 40 V, TJ = 25C) Input Bias Current (VFB = 2.6 V)
Regline IIB
mV nA dB
500 -
Open Loop Voltage Gain (TJ = 25C)
AVOL
2. Tested junction temperature range for the MC33363A: Tlow = -25C Thigh = +125C
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2. Tested junction temperature range for the MC33363A: Tlow = -25C Thigh = +125C TOTAL DEVICE (Pin 3) UNDERVOLTAGE LOCKOUT (Pin 3) STARTUP CONTROL (Pin 1) OVERCURRENT COMPARATOR (Pin 16) POWER SWITCH (Pin 16) PWM COMPARATOR (Pins 7, 9) OVERVOLTAGE DETECTION (Pin 11) ERROR AMPLIFIER (Pins 9, 10)
ELECTRICAL CHARACTERISTICS (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin8 = 1.0 mF, for typical values TJ = 25C, for min/max
values TJ is the operating junction temperature range that applies (Note 2), unless otherwise noted)
Power Supply Current Startup (VCC = 10 V, Pin 1 Open) Operating
Minimum Operating Voltage After Turn-On
Startup Threshold (VCC Increasing)
Off-State Leakage Current (Vin = 50 V, VCC = 20 V)
Peak Startup Current (Vin = 50 V) (TJ = -25C to 100C) VCC = 0 V VCC = (Vth(on) - 0.2 V)
Current Limit Threshold (RT = 13 k)
Fall Time
Rise Time
Drain-Source Off-State Leakage Current (VDS = 650 V) TJ = 25C TJ = Tlow to Thigh
Drain-Source On-State Resistance (ID = 200 mA) TJ = 25C TJ = Tlow to Thigh
Duty Cycle Maximum (VFB = 0 V) Minimum (VFB = 2.7 V)
Input Bias Current (Vin = 2.6 V)
Input Threshold Voltage
Output Voltage Swing High State (ISource = 100 mA, VFB < 2.0 V) Low State (ISink = 100 mA, VFB > 3.0 V)
Gain Bandwidth Product (f = 100 kHz, TJ = 25C)
Characteristic
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MC33363A
3 Symbol VCC(min) DC(max) DC(min) RDS(on) Vth(on) GBW ID(off) ID(off) VOH VOL Istart ICC Vth Ilim IIB tr tf 2.47 Min 7.5 2.0 2.0 0.7 4.0 - 48 - 11 - - - - - - - - - - - 0.27 3.4 14.9 0.25 - 100 Typ 9.5 5.0 5.0 0.9 7.5 - 2.6 5.3 0.2 1.0 40 50 50 50 0 - 0.35 2.73 11.5 Max 200 500 0.5 5.0 8.0 8.0 1.1 1.0 50 9.0 20 18 52 0 - - - MHz Unit mA mA nA mA mA ns ns % W V V A V V
MC33363A
I PK, POWER SWITCH PEAK DRAIN CURRENT (A 1.0 M f OSC, OSCILLATOR FREQUENCY (Hz)
CT = 100 pF
500 k C = 200 pF T 200 k CT = 500 pF 100 k 50 k 20 k
CT = 1.0 nF CT = 2.0 nF
VCC = 20 V TA = 25C
1.5 1.0 0.8 0.6 0.4 0.3 0.2 0.15 7.0 Inductor supply voltage and inductance value are adjusted so that Ipk turn-off is achieved at 5.0 ms. 10 15 20 30 40 50 70 VCC = 20 V CT = 1.0 mF TA = 25C
CT = 5.0 nF CT = 10 nF
10 k 7.0
10
15
20
30
50
70
RT, TIMING RESISTOR (kW)
RT, TIMING RESISTOR (kW)
Figure 2. Oscillator Frequency versus Timing Resistor
Figure 3. Power Switch Peak Drain Current versus Timing Resistor
Dmax, MAXIMUM OUTPUT DUTY CYCLE (%)
0.8 I chg /I dscg , OSCILLATOR CHARGE/DISCHARGE CURRENT (mA) 0.5 VCC = 20 V TA = 25C
70
RD/RT Ratio Discharge Resistor Pin 7 to GND
VCC = 20 V CT = 2.0 nF TA = 25C
60
0.3 0.2 0.15 0.1 0.08 7.0 10 15 20 30 50 70
50
40
30 1.0
RC/RT Ratio Charge Resistor Pin 7 to Vreg 2.0 3.0 5.0 7.0 10 TIMING RESISTOR RATIO
RT, TIMING RESISTOR (kW)
Figure 4. Oscillator Charge/Discharge Current versus Timing Resistor
Figure 5. Maximum Output Duty Cycle versus Timing Resistor Ratio
80 Gain 60 Phase 40 20 0 -20 10
VCC = 20 V VO = 1.0 to 4.0 V RL = 5.0 MW CL = 2.0 pF TA = 25C
, EXCESS PHASE (DEGREES) Vsat , OUTPUT SATURATION VOLTAGE (V)
A VOL, OPEN LOOP VOLTAGE GAIN (dB)
100
0 30 60 90
0 -1.0 Source Saturation (Load to Ground) Vref
- 2.0
120 150 180 10 M
2.0 1.0
Sink Saturation (Load to Vref) GND
VCC = 20 V TA = 25C
100
1.0 k
10 k
100 k
1.0 M
0
0
0.2
0.4
0.6
0.8
1.0
f, FREQUENCY (Hz)
IO, OUTPUT LOAD CURRENT (mA)
Figure 6. Error Amp Open Loop Gain and Phase versus Frequency
Figure 7. Error Amp Output Saturation Voltage versus Load Current
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MC33363A
VCC = 20 V AV = -1.0 CL = 10 pF TA = 25C 20 mV/DIV VCC = 20 V AV = -1.0 CL = 10 pF TA = 25C 0.5 V/DIV 1.0 ms/DIV
1.80 V
3.00 V
1.75 V
1.75 V
1.70 V
0.50 V
1.0 ms/DIV
Figure 8. Error Amplifier Small Signal Transient Response
Figure 9. Error Amplifier Large Signal Transient Response
V reg, REGULATOR VOLTAGE CHANGE (mV)
0 Istart, STARTUP CURRENT (mA) VCC = 20 V RT = 10 k TA = 25C
8 7 6 5 4 3 2 1 0 0 2 4 6 8 10 VCC, SUPPLY VOLTAGE (V) 12 14 VPin1 = 50 V TA = 25C
-20
-40
-60
-80
0
4.0
8.0
12
16
20
Ireg, REGULATOR SOURCE CURRENT (mA)
Figure 10. Regulator Output Voltage Change versus Source Current
Figure 11. Peak Startup Current versus Power Supply Voltage
8 Istart, STARTUP CURRENT (mA) 7 6 5 4 3 2 1 0 0 10 20 30 40 50 VCC = 14 V TA = 25C VCC = 0 V TA = 25C
VPin1, STARTUP PIN VOLTAGE (V)
Figure 12. Peak Startup Current versus Startup Input Voltage
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MC33363A
R DS(on), DRAIN-SOURCE ON-RESISTANCE ( ) 32 24 16 8.0 4.0 0 -50 COSS, DRAIN-SOURCE CAPACITANCE (pF) 160 VCC = 20 V TA = 25C 120
ID = 200 mA
80
40 COSS measured at 1.0 MHz with 50 mVpp. 10 100 1000 VDS, DRAIN-SOURCE VOLTAGE (V)
Pulse tested at 5.0 ms with < 1.0% duty cycle so that TJ is as close to TA as possible. -25 0 25 50 75 100 125 150
0 1.0
TA, AMBIENT TEMPERATURE (C)
Figure 13. Power Switch Drain-Source On-Resistance versus Temperature
Figure 14. Power Switch Drain-Source Capacitance versus Voltage
3.6 I CC, SUPPLY CURRENT (mA) 3.2 2.4 1.6 0.8
CT = 390 pF CT = 2.0 nF
100 R JA , THERMAL RESISTANCE JUNCTION-TO-AIR ( C/W) L = 12.7 mm of 2.0 oz. copper. Refer to Figures 17 and 18.
10
0
RT = 10 k Pin 1 = Open Pin 4, 5, 10, 11, 12, 13 = GND TA = 25C 0 10 20 VCC, SUPPLY VOLTAGE (V) 30 40
1.0 0.01
0.1
1.0 t, TIME (s)
10
100
Figure 15. Supply Current versus Supply Voltage
Figure 16. DW and P Suffix Transient Thermal Resistance
R JA , THERMAL RESISTANCE JUNCTION-TO-AIR ( C/W)
R JA, THERMAL RESISTANCE JUNCTION-TO-AIR ( C/W)
80 60 40 20 PD(max) for TA = 70C RqJA
L
80 70 60 50 RqJA 40 30 0 10 20
Printed circuit board heatsink example
2.0 1.6 1.2 0.8 0.4
L
2.0 oz Copper
L 3.0 mm Graphs represent symmetrical layout
L 3.0 mm Graphs represent symmetrical layout
30
40
0 50
0
0
10
20
30
L, LENGTH OF COPPER (mm)
L, LENGTH OF COPPER (mm)
Figure 17. DW Suffix (SOP-16L) Thermal Resistance and Maximum Power Dissipation versus P.C.B. Copper Length
Figure 18. P Suffix (DIP-16) Thermal Resistance and Maximum Power Dissipation versus P.C.B. Copper Length
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IIIII IIIII
2.0 oz Copper
90
PD(max) for TA = 50C
Printed circuit board heatsink example
2.4
4.0 3.0 2.0 1.0 0
40
50
P D , MAXIMUM POWER DISSIPATION (W)
PD, MAXIMUM POWER DISSIPATION (W)
100
2.8
100
5.0
IIIII IIIII
MC33363A
PIN FUNCTION DESCRIPTION
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1 Startup Input This pin connects directly to the rectified ac line voltage source. Internally Pin 1 is tied to the drain of a high voltage startup MOSFET. During startup, the MOSFET supplies internal bias, and charges an external capacitor that connects from the VCC pin to ground. 2 3 - This pin has been omitted for increased spacing between the rectified ac line voltage on Pin 1 and the VCC potential on Pin 3. VCCCC This is the positive supply voltage input. During startup, power is supplied to this input from Pin 1. When VCC reaches the UVLO upper threshold, the startup MOSFET turns off and power is supplied from an auxiliary transformer winding. These pins are the control circuit grounds. They are part of the IC lead frame and provide a thermal path from the die to the printed circuit board. 4, 5, 12, 13 6 7 8 9 GND RT Resistor RT connects from this pin to ground. The value selected will program the Current Limit Comparator threshold and affect the Oscillator frequency. CT Capacitor CT connects from this pin to ground. The value selected, in conjunction with resistor RT, programs the Oscillator frequency. Regulator Output Compensation This 6.5 V output is available for biasing external circuitry. It requires an external bypass capacitor of at least 1.0 mF for stability. This pin is the Error Amplifier output and is made available for loop compensation. It can be used as an input to directly control the PWM Comparator. This is the inverting input of the Error Amplifier. It has a 2.6 V threshold and normally connects through a resistor divider to the converter output, or to a voltage that represents the converter output. 10 Voltage Feedback Input Overvoltage Protection Input 11 This input provides runaway output voltage protection due to an external component or connection failure in the control loop feedback signal path. It has a 2.6 V threshold and normally connects through a resistor divider to the converter output, or to a voltage that represents the converter output. These pins have been omitted for increased spacing between the high voltages present on the Power Switch Drain, and the ground potential on Pins 12 and 13. This pin is designed to directly drive the converter transformer and is capable of switching a maximum of 700 V and 1.0 A. 14, 15 16 - Power Switch Drain
Pin
Function
Description
ORDERING INFORMATION
Device MC33363ADW MC33363ADWG MC33363ADWR2 MC33363ADWR2G MC33363AP MC33363APG Package SOIC-16WB SOIC-16WB (Pb-Free) SOIC-16WB SOIC-16WB (Pb-Free) PDIP-16 PDIP-16 (Pb-Free) Shipping 47 Units / Rail 47 Units / Rail 1000 / Tape & Reel 1000 / Tape & Reel 25 Units / Rail 25 Units / Rail
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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MC33363A
AC Input Startup Input Current Mirror Startup Control Band Gap Regulator 2.25 I UVLO 14.5 V/ 9.5 V OVP PWM Latch S Q PWM Comparator R Leading Edge Blanking 6.0 Current Limit Comparator Compensation 450 2.6 V 10 Voltage Feedback Input 9 Error Amplifier Driver 2.6 V 16 Power Switch Drain 1
Regulator Output 6.5 V 8 I 6 RT CT
VCC 3 Overvoltage Protection Input 11 DC Output
4I Oscillator 7
Thermal Shutdown
270 A Gnd 4, 5, 12, 13
Figure 19. Representative Block Diagram
Capacitor CT Compensation Oscillator Output PWM Comparator Output PWM Latch Q Output Power Switch Gate Drive Leading Edge Blanking Input (Power Switch Drain Current) Normal PWM Operating Range Output Overload
2.6 V 0.6 V
Current Limit Propagation Delay Current Limit Threshold
Figure 20. Timing Diagram
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MC33363A
OPERATING DESCRIPTION
Introduction
The MC33363A represents a new higher level of integration by providing all the active high voltage power, control, and protection circuitry required for implementation of a flyback or forward converter on a single monolithic chip. This device is designed for direct operation from a rectified 240 Vac line source and requires a minimum number of external components to implement a complete converter. A description of each of the functional blocks is given below, and the representative block and timing diagrams are shown in Figures 19 and 20.
Oscillator and Current Mirror
The formula for the charge/discharge current along with the oscillator frequency are given below. The frequency formula is a first order approximation and is accurate for CT values greater than 500 pF. For smaller values of CT, refer to Figure 2. Note that resistor RT also programs the Current Limit Comparator threshold.
I 5.4 +R chg dscg T I f[ chg dscg 4C T
PWM Comparator and Latch
The oscillator frequency is controlled by the values selected for the timing components RT and CT. Resistor RT programs the oscillator charge/discharge current via the Current Mirror 4 I output, Figure 4. Capacitor CT is charged and discharged by an equal magnitude internal current source and sink. This generates a symmetrical 50% duty cycle waveform at Pin 7, with a peak and valley threshold of 2.6 V and 0.6 V respectively. During the discharge of CT, the oscillator generates an internal blanking pulse that holds the inverting input of the AND gate driver high. This causes the Power Switch gate drive to be held in a low state, thus producing a well controlled amount of output deadtime. The amount of deadtime is relatively constant with respect to the oscillator frequency when operating below 1.0 MHz. The maximum Power Switch duty cycle at Pin 16 can be modified from the internal 50% limit by providing an additional charge or discharge current path to CT, Figure 21. In order to increase the maximum duty cycle, a discharge current resistor RD is connected from Pin 7 to ground. To decrease the maximum duty cycle, a charge current resistor RC is connected from Pin 7 to the Regulator Output. Figure 5 shows an obtainable range of maximum output duty cycle versus the ratio of either RC or RD with respect to RT.
Current Mirror 2.25 I I RC RT 4I CT 7 Oscillator Blanking Pulse 6 Current Limit Reference
The pulse width modulator consists of a comparator with the oscillator ramp voltage applied to the non-inverting input, while the error amplifier output is applied into the inverting input. The Oscillator applies a set pulse to the PWM Latch while CT is discharging, and upon reaching the valley voltage, Power Switch conduction is initiated. When CT charges to a voltage that exceeds the error amplifier output, the PWM Latch is reset, thus terminating Power Switch conduction for the duration of the oscillator ramp-up period. This PWM Comparator/Latch combination prevents multiple output pulses during a given oscillator clock cycle. The timing diagram shown in Figure 20 illustrates the Power Switch duty cycle behavior versus the Compensation voltage.
Current Limit Comparator and Power Switch
Regulator Output 1.0 8
RD
The MC33363A uses cycle-by-cycle current limiting as a means of protecting the output switch transistor from overstress. Each on-cycle is treated as a separate situation. Current limiting is implemented by monitoring the output switch current buildup during conduction, and upon sensing an overcurrent condition, immediately turning off the switch for the duration of the oscillator ramp-up period. The Power Switch is constructed as a SENSEFET allowing a virtually lossless method of monitoring the drain current. It consists of a total of 2819 cells, of which 65 are connected to a 6.0 W ground-referenced sense resistor. The Current Sense Comparator detects if the voltage across the sense resistor exceeds the reference level that is present at the inverting input. If exceeded, the comparator quickly resets the PWM Latch, thus protecting the Power Switch. The current limit reference level is generated by the 2.25 I output of the Current Mirror. This current causes a reference voltage to appear across the 450 W resistor. This voltage level, as well as the Oscillator charge/discharge current are both set by resistor RT. Therefore when selecting the values for RT and CT, RT must be chosen first to set the Power Switch peak drain current, while CT is chosen second to set the desired Oscillator frequency. A graph of the Power Switch peak drain current versus RT is shown in Figure 3 with the related formula below.
I pk + 15.95 T - 1.14 1000 R
PWM Comparator
Figure 21. Maximum Duty Cycle Modification
The Power Switch is designed to directly drive the converter transformer and is capable of switching a
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MC33363A
maximum of 700 V and 1.0 A. Proper device voltage snubbing and heatsinking are required for reliable operation. A Leading Edge Blanking circuit was placed in the current sensing signal path. This circuit prevents a premature reset of the PWM Latch. The premature reset is generated each time the Power Switch is driven into conduction. It appears as a narrow voltage spike across the current sense resistor, and is due to the MOSFET gate to source capacitance, transformer interwinding capacitance, and output rectifier recovery time. The Leading Edge Blanking circuit has a dynamic behavior in that it masks the current signal until the Power Switch turn-on transition is completed. The current limit propagation delay time is typically 300 ns. This time is measured from when an overcurrent appears at the Power Switch drain, to the beginning of turn-off.
Error Amplifier Startup Control
An internal Startup Control circuit with a high voltage enhancement mode MOSFET is included within the MC33363A. This circuitry allows for increased converter efficiency by eliminating the external startup resistor, and its associated power dissipation, commonly used in most off-line converters that utilize a UC3842 type of controller. Rectified ac line voltage is applied to the Startup Input, Pin 1. This causes the MOSFET to enhance and supply internal bias as well as charge current to the VCC bypass capacitor that connects from Pin 3 to ground. When VCC reaches the UVLO upper threshold of 15.2 V, the IC commences operation and the startup MOSFET is turned off. Operating bias is now derived from the auxiliary transformer winding, and all of the device power is efficiently converted down from the rectified ac line.
Regulator
An fully compensated Error Amplifier with access to the inverting input and output is provided for primary side voltage sensing, Figure 19. It features a typical dc voltage gain of 82 dB, and a unity gain bandwidth of 1.0 MHz with 78 degrees of phase margin, Figure 6. The noninverting input is internally biased at 2.6 V 3.1% and is not pinned out. The Error Amplifier output is pinned out for external loop compensation and as a means for directly driving the PWM Comparator. The output was designed with a limited sink current capability of 270 mA, allowing it to be easily overridden with a pull-up resistor. This is desirable in applications that require secondary side voltage sensing, Figure 22. In this application, the Voltage Feedback Input is connected to the Regulator Output. This disables the Error Amplifier by placing its output into the sink state, allowing the optocoupler transistor to directly control the PWM Comparator.
Overvoltage Protection
A low current 6.5 V regulated output is available for biasing the Error Amplifier and any additional control system circuitry. It is capable of up to 10 mA and has short-circuit protection. This output requires an external bypass capacitor of at least 1.0 mF for stability.
Thermal Shutdown and Package
An Overvoltage Protection Comparator is included to eliminate the possibility of runaway output voltage. This condition can occur if the control loop feedback signal path is broken due to an external component or connection failure. The comparator is normally used to monitor the primary side VCC voltage. When the 2.6 V threshold is exceeded, it will immediately turn off the Power Switch, and protect the load from a severe overvoltage condition. This input can also be driven from external circuitry to inhibit converter operation.
Undervoltage Lockout
An Undervoltage Lockout (UVLO) comparator has been incorporated to guarantee that the integrated circuit has sufficient voltage to be fully functional before the output stage is enabled. The UVLO comparator monitors the VCC voltage at Pin 3 and when it exceeds 14.5 V, the reset signal is removed from the PWM Latch allowing operation of the Power Switch. To prevent erratic switching as the threshold is crossed, 5.0 V of hysteresis is provided.
Internal thermal circuitry is provided to protect the Power Switch in the event that the maximum junction temperature is exceeded. When activated, typically at 155C, the Latch is forced into a `reset' state, disabling the Power Switch. The Latch is allowed to `set' when the Power Switch temperature falls below 145C. This feature is provided to prevent catastrophic failures from accidental device overheating. It is not intended to be used as a substitute for proper heatsinking. The MC33363A is contained in a heatsinkable plastic dual-in-line package in which the die is mounted on a special heat tab copper alloy lead frame. This tab consists of the four center ground pins that are specifically designed to improve thermal conduction from the die to the circuit board. Figures 17 and 18 show a simple and effective method of utilizing the printed circuit board medium as a heat dissipater by soldering these pins to an adequate area of copper foil. This permits the use of standard layout and mounting practices while having the ability to halve the junction to air thermal resistance. The examples are for a symmetrical layout on a single-sided board with two ounce per square foot of copper. Figure 23 shows a practical example of a printed circuit board layout that utilizes the copper foil as a heat dissipater. Note that a jumper was added to the layout from Pins 8 to 10 in order to enhance the copper area near the device for improved thermal conductivity. The application circuit requires two ounce copper foil in order to obtain 8.0 W of continuous output power at room temperature.
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MC33363A
F1 1.0 A D4 92 to 276 Vac Input D2 D3 1N4006 D1 1 Startup Mirror C4 1.0 R1 13 k C3 1200 pF 7 Osc PWM Latch Driver Q PWM R LEB ILimit Thermal 9 270 A 4, 5, 12, 13 2.6 V EA 10 IC1 MC33363A R2 2.7 k 4 5 8 6 Reg UVLO 14.5 V/ 9.5 V OVP 2.6 V 16 S 3 C2 10 R4 5.1 k R3 1.0 k C1 47 C5 4.0 nF R6 180 k 1.0 W D5 MUR 1100E C6 47 pF R7 2.2 k 1.0 W D6 R5 MUR 39 120 D7 T1 MBR 1635 C9 C10 330 330 L1 5.0 H 5.05 V/3.0 A DC Output
+
11
C8 330
1 2
R8 220 R9 2.80 k C7 100 nF 1
C11 220 C12 1.0
-
IC2 3 MOC 8103 IC3 TL431B 2
R10 2.74 k
Figure 22. 15 W Off-Line Converter Table 1. CONVERTER TEST DATA
Test Line Regulation Load Regulation Conditions Vin = 92 Vac to 276 Vac, IO 3.0 A Vin = 115 Vac, IO = 0.75 A to 3.0 A D = 1.0 mV D = 5.0 mV Results
Vin = 230 Vac, IO = 0.75 A to 3.0 A
Output Ripple Vin = 115 Vac, IO = 3.0 A
D = 5.0 mV
Triangular = 2.0 mVpp, Spike = 32 mVpp
Vin = 230 Vac, IO = 3.0 A
Efficiency Vin = 115 Vac, IO = 3.0 A
Triangular = 2.0 mVpp, Spike = 34 mVpp
76.8%*
Vin = 230 Vac, IO = 3.0 A
76.8%
This data was taken with the components listed below mounted on the printed circuit board shown in Figure 23. *With MBR2535CTL, 78.8% efficiency. PCB layout modification is required to use this rectifier. For high efficiency and small circuit board size, the Sanyo Os-Con capacitors are recommended for C8, C9, C10 and C11. C8, C9, C10 = Sanyo Os-Con #6SA330M, 330 mF 6.3 V. C11 = Sanyo Os-Con #10SA220M, 220 mF 10 V. L1 = Coilcraft S5088-A, 5.0 mH, 0.11 W. T1 = Coilcraft U6875-A Primary: 77 turns of # 28 AWG, Pin 1 = start, Pin 8 = finish. Two layers 0.002 Mylar tape. Secondary: 5 turns of # 22 AWG, 2 strands bifiliar wound, Pin 5 = start, Pin 4 = finish. Two layers 0.002 Mylar tape. Auxiliary: 13 turns of # 28 AWG wound in center of bobbin, Pin 2 = start, Pin 7 = finish. Two layers 0.002 Mylar tape. Gap: 0.011 total for a primary inductance (LP) of 620 mH. Core and Bobbin: Coilcraft PT1950, E187, 3F3 material.
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MC33363A
Caution! High Voltages
D1 D2 F1 IC1 L1 R1 R2 DC Output C4 C3 J1 R3 R3 IC2 C7 IC3 R10 R9 C12
C11
AC Line Input D3 D4
R4 C2 D6 R5
R8
C10
D5
R7 T1
C9
C1
R6 D7 C5 C6 1 (Top View) 2.75" C8
MC33363A
2.25"
(Bottom View)
Figure 23. Printed Circuit Board and Component Layout (Circuit of Figure 22) http://onsemi.com
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MC33363A
PACKAGE DIMENSIONS
PDIP-16 P SUFFIX CASE 648E-01 ISSUE O
-A- R
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION A AND B DOES NOT INCLUDE MOLD PROTRUSION. 5. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.25 (0.010). 6. ROUNDED CORNER OPTIONAL. DIM A B C D F G H J K L M P R S INCHES MIN MAX 0.740 0.760 0.245 0.260 0.145 0.175 0.015 0.021 0.050 0.070 0.100 BSC 0.050 BSC 0.008 0.015 0.120 0.140 0.295 0.305 0_ 10 _ 0.200 BSC 0.300 BSC 0.015 0.035 MILLIMETERS MIN MAX 18.80 19.30 6.23 6.60 3.69 4.44 0.39 0.53 1.27 1.77 2.54 BSC 1.27 BSC 0.21 0.38 3.05 3.55 7.50 7.74 0_ 10 _ 5.08 BSC 7.62 BSC 0.39 0.88
M -B- L
1
8
P
F
J
C S H G D 13 PL 0.25 (0.010)
M
-T-
SEATING PLANE
K
TB
S
A
S
SO-16W DW SUFFIX CASE 751N-01 ISSUE O
-A- T
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R S T MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 2.54 BSC 3.81 BSC INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 0.100 BSC 0.150 BSC
-B-
1 8
P
0.010 (0.25)
M
B
M
13X
D
M
J TA
S
0.010 (0.25)
B
S
F R X 45_ C -T- S K
9X SEATING PLANE
M
G
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MC33363A
The product described herein (MC33363A), may be covered by one or more of the following U.S. patents: 4,553,084; 5,418,410; 5,477,175. There may be other patents pending. SENSEFET is a trademark of Semiconductor Components Industries, LLC (SCILLC)
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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14
MC33363A/D

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